The SKY53510/80/40 series from Skyworks lets you distribute clocks to devices such as SerDes for high-speed serial links.
Skyworks has released its SKY53510/80/40 family of Low-Power DC to 3.1 GHz Ultra-Low Additive Jitter Differential Clock Buffers. These devices help engineers design clocking networks for high-speed buses used in PCIe Gen 7 5G/6G, AI, and cloud-based network equipment. The company claims these devices set a new benchmark in ultra-low jitter clock buffers.
Ultra-low additive jitter at 156.25 MHz LVPECL, 12 kHz to 20 MHz comes in at 35 fs RMS typical, – 47 fs RMS max. The low jitter simplifies design and enhances signal integrity.
As the block diagram shows, the SKY53510/80/40 family features a 3:1 input multiplexer (including crystal input), one single-ended output, and up to ten differential outputs. Offered in compact thermally enhanced QFN packages — 7×7 mm (10 outputs), 6×6 mm (8 outputs), and 5×5 mm (4 outputs). The devices are pin-compatible with industry-standard layouts.
Applications include:
- PCIe Gen 3 through Gen 7
- 56G/112G/224G SerDes
- 5G/6G mMIMO radio systems
- SyncE and broadcast video
- Medical imaging
- Aerospace/defense
Other features include:
- Universal format translation: LVPECL, LVCMOS, LVDS, HCSL, CML, SSTL, HSTL, and AC-coupled single-ended inputs; selectable LVPECL, LVDS, HCSL, or tristate outputs
- Low power operation: Separate core/output voltage supplies (1.8V, 2.5V, 3.3V)
- Integrated LDOs: >70 dBc PSRR for noisy environments
- Wide temperature range: -40°C to +95°C ambient (-40°C to +105°C board)
- Low noise floor: -166 dBc/Hz for SyncE 156.25 MHz applications
According to Skyworks, the clock buffers are available now for samples and in production quantities. The company also offers a SKY53510-EVB development kit.
